The present invention relates to a semiconductor memory device and, more particularly, it relates to a stack-type DRAM (Dynamic Random Access Memory) device having a charge-storage electrode above its bit lines.
Among semiconductor memory devices in which higher integration has been pursued, DRAMs require the finest processing techniques. To obtain sufficient capacitance for storing charge, DRAMs use trench-type cells having charge-storage electrodes which are formed in trenched portions of the semiconductor substrate or stack-type cells having charge-storage electrodes which are stacked three-dimensionally on the semiconductor substrate. As smaller features are defined in a stack-type cell, the charge-storage electrodes formed therein inevitably extend upward in order to obtain sufficient charge-storage capacitance.
However, with lithographic techniques for forming patterns, the depth of focus becomes shallower as the resolution limit becomes smaller. In general, the resolution limit is proportional to the wavelength of the light source in use, while it is inversely proportional to the numerical aperture of the lens of an aligner. To form a micropattern, therefore, it is necessary to use a shorter wavelength for the light source or to increase the numerical aperture of the lens.
On the other hand, since the depth of focus is proportional to the wavelength of the light source, while it is inversely proportional to the square of the numerical aperture of the lens, the depth of focus becomes shallower as the resolution limit becomes smaller. To form a micropattern, therefore, it is necessary to minimize the difference in level of the semiconductor substrate.
Below, a method of manufacturing a DRAM which uses the conventional stack-type cells mentioned above will be described with reference to drawings.
FIGS. 12 to 15 are cross sections illustrating steps according to the method of manufacturing the DRAM device using the conventional stack-type memory cells. In the drawings, 5 denotes a gate electrode which is connected to the word line, 9 denotes a bit line, and 14 denotes a charge-storage electrode.
First, as shown in FIG. 12, an insulating film for isolation 2 is formed on a p-type semiconductor substrate 1. Then, a gate insulating film 4 constituting a switching transistor, the gate electrode 5 connected to a word line, an on-gate insulating film 6, and a side-wall insulating film 7 are sequentially formed. Thereafter, the bit line 9 is formed on the side faces of the gate electrode 5, followed by the deposition of a first BPSG film 18 serving as an insulating film. The resulting first BPSG film 18 is annealed for planarization by using a reflow technique. Subsequently, a resist pattern 12 is deposited on the first BPSG film 18 so that an opening 13 for a charge-storage electrode 13 (See FIG. 13), which will be described later, is formed above the other n-type diffused region 3b.
Next, as shown in FIG. 13, the opening 13 for a charge-storage electrode is formed in the first BPSG film 18 by using the resist pattern as the etching mask, followed by the deposition of the charge-storage electrode 14 through the opening 13 for a charge-storage electrode 14.
Next, as shown in FIG. 14, a capacitance insulating film 15 consisting of multiple layers of a silicon nitride film and a silicon dioxide film, and a plate electrode 16 are formed over a memory cell array region 40.
Next, as shown in FIG. 15, after a second BPSG film 19 is deposited as an interlayer insulating film, the second BPSG film 19 is annealed for planarization by using a reflow technique, thereby reducing the maximum tilt angle of a step region 50 of the second BPSG film 19 between the memory cell array region 40 and a peripheral circuit region 30.
In a 64M-bit DRAM, for example, a storage capacitance of about 30 fF is required in order to obtain a satisfactory storage electrode. To meet the requirement, the charge-storage electrode 14 should be as high as about 800 nm in the case of using a capacitance insulating film having a memory cell area of 1.5 .mu.m.sup.2 and a thickness corresponding to 6 nm if calculated with a SiO.sub.2 film.
However, with the foregoing structure, if a polycrystal silicon film having a thickness of 200 nm is used as the plate electrode 16, there arises a difference in level of about 1 .mu.m, which is the sum of the height of the charge-storage electrode 14 of 800 nm and the film thickness of the plate electrode 16 of 200 nm, between the memory cell array region 40 and peripheral circuit region 30. Consequently, a sufficient planarizing effect is not obtained in the step region 50 only by making the second BPSG film 19 reflow.
This renders the subsequent formation of a wiring pattern thereon extremely difficult. Although a pattern as small as 0.35 .mu.m is required to be formed in the 64M-bit DRAM, the depth of focus becomes shallower as the pattern becomes smaller with a photolithographic technique, so that it becomes difficult to form a micropattern over a region with a large difference in level.
With the structure in which the charge-storage electrode 14 is formed above the bit line 9, the opening 13 for a charge-storage electrode should be formed in a small region between the bit lines 9 and between the gate electrodes 5 (word lines), so that high precision for mask alignment and a technique for forming a micropattern are required in the photolithographic process.